
CY284108
...................... Document #: 38-07713 Rev. *B Page 10 of 16
FS_A, FS_B,FS_C
VTT_PWRGD#
PWRGD_VRM
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
0.2-0.3 ms
Delay
State 0
State 2
State 3
Wait for
VTT_PWRGD#
Sample Sels
Off
On
State 1
Device is not affected,
VTT_PWRGD# is ignored
Figure 6. VTT_PWRGD# Timing Diagram
VTT_PWRGD# = Low
Delay >
0.25 ms
S1
Power Off
S0
VDD_A = 2.0V
Sample
Inputs straps
S2
Normal
Operation
Wait for <1.8 ms
Enable Outputs
S3
VTT_PWRGD# = toggle
VDD_A = off
Figure 7. Clock Generator Power-up/Run State Diagram